1. Field of the Invention
The present invention relates to a semiconductor device and a forming method thereof, in particular, to a complementary metal-oxide-semiconductor device and a fabrication method thereof.
2. Description of Related Art
At present, a method of fabricating a source/drain (S/D) region of a complementary metal-oxide-semiconductor (MOS) transistor using a SiGe technique has been proposed to increase mobility of electrons and holes for improving the performance of devices.
Generally, the method applying the SiGe technique to manufacturing a complementary metal-oxide semiconductor (CMOS) device comprises steps of forming a P-type gate structure and an N-type gate structure on the substrate and then forming a spacer and a lightly-doped drain (LDD) sequentially. Thereafter, a high-temperature oxide (HTO) layer is formed on the entire substrate. After that, a portion of HTO layer on the PMOS transistor region is removed by using a patterned photoresist layer as a mask, so as to expose a surface of the substrate where the S/D region of the PMOS transistor region will be subsequently formed. Meanwhile, a portion of the HTO layer remains on the P-type gate structure and the spacer which is located on the sidewall of the P-type gate structure so as to achieve the function for protecting the gate structure and the spacer. Next, the patterned photoresist layer is removed. Subsequently, the exposed substrate is removed to form a trench. Finally, a SiGe layer is formed in the trench to serve as the S/D region of the PMOS transistor.
However, in the steps of removing the patterned photoresist layer, forming the trench in the PMOS transistor region, and the step of a pre-clean process or a pre-bake process to be performed, the portion of the HTO layer on the P-type gate structure is remove and even a portion of the HTO layer on the IQMOS transistor region is removed to expose the surface of the P-type gate structure and a portion of the substrate surface of the NMOS transistor region. Therefore, when a SiGe process is performed to form the SiGe layer filling in the trench, the SiGe layer is also formed on the exposed substrate surface and the top of the P-type gate structure, i.e., a so-called “poly bump”, which seriously affects reliability and performance of devices.
Some US patents also disclose the aforementioned relevant technologies, such as U.S. Pat. No. 6,573,172B1 and U.S. Pat. No. 6,858,506B2. The aforementioned documents are both reference materials of the present invention.